There is a continuing trend within the microelectronics industry to incorporate more circuitry having greater complexity on a single integrated circuit (IC) chip. Maintaining this trend generally entails shrinking the size of individual devices within the circuit by reducing the critical dimensions (CDs) of device elements along with the pitch, or the CD of such an element added to the spacing between elements. Microlithography tooling and processing techniques play an important role in resolving the features necessary to fabricate devices and accordingly, are continually under development to meet industry milestones relating to the CD and pitch characteristic of each new technology generation.
High numerical aperture (NA) projection stepper/scanner systems in combination with advanced photoresist processes now are capable of routinely resolving complex patterns that include isolated and dense resist features having CDs and pitches, respectively, well below the exposure wavelength. However, to meet the requirements of device design rules which continue to push the resolution limits of existing processes and tooling, other more specialized techniques have been developed to further enhance resolution. These include double patterning technology (DPT) techniques in which device patterns having potentially optically unresolvable features are decomposed into two or more complementary, and more easily resolvable patterns, each containing features with larger CDs and/or a relaxed pitch.
Generating high-volume, production-grade, DPT-compliant layout designs requires a significant change to the traditional physical design flow, in which layout designers use an iterative methodology to generate design rule check (DRC)-clean layouts to be processed by Mask Data Preparation (MDP). In the existing DPT-compliant design flow, layout designs are required to pass not only DRCs but also DPT-compliance checks. FIG. 1 depicts an existing DPT-compliant flow that includes additional rule-based checks for DPT-compliance. As shown therein, a drawn one-color layout (151) is checked for DRC and DPT compliance (153). If the design passes, an MDP-ready layout (two-color) is generated (152). If the design fails, an automated decomposition process (154) decomposes the design, and a post-decomposed layout is generated (155). Again, a DRC and DPT compliance check is performed (157), and if the design now passes, an MDP-ready layout (two-color) is generated (156). If the design again fails, a manual fix may be performed (158), and a modified layout generated (159), wherein the compliance checks are run again from step 153, as shown.
It will be appreciated that passing DPT-compliance checks often requires layouts to be decomposed (step 154). The decomposition process that includes cutting and stitching can be automated using state-of-the-art electronic design automation (EDA) decomposition tools. However, due to the complexity of mask-layer assignments, cuts, stitch-region generation, and design rule interactions, EDA tools cannot identify all possible decomposition solutions such that DPT-compliance check violations (i.e., failure at step 157) can be resolved automatically. For example, FIGS. 2a and 2b show spacing violations (marked by an “X”) in non-decomposed layouts (parts 210 and 230) that must then be decomposed through manual decomposition (parts 220 and 240). Thus, layout designers are encumbered with fixing hundreds to thousands of DPT-compliant-check violations that need to be resolved through manual decomposition, cutting, and stitching.